The present application has Government rights assigned to the National Science Foundation under contract numbers ECS-9622134 and ECS-9624160, and assigned to DARPA/AFOSR under contract number F49620-96-C-0006.
A. Field of the Invention
The present invention relates generally to interband tunneling diodes, and, more particularly to Si-based resonant interband tunneling diodes and a method of making interband tunneling diodes.
B. Description of the Related Art
The purpose of this invention is the development of a tunnel diode exhibiting negative differential resistance (NDR) at room temperature on a Si platform. It has been demonstrated that tunnel diode/transistor logic, realized to date only in III-V material systems, enhances any transistor technology [1,2] by reducing the number of components per circuit function, increasing speed, and lowering power consumption. As an example of how tunnel diodes are beneficial, a tunneling static random access memory (T-SRAM) [3,4] exhibits reduced power consumption with a concurrent area reduction as compared to conventional static random access memory (SRAM) or dynamic random access memory (DRAM) cells. Depending on the circuit considered, one of three different performance gains or a combination thereof may be expected: (i) increased circuit speed, (ii) reduced circuit component counts/footprint areas, or (iii) reduced power dissipation.
With the exception of Si Esaki diodes fabricated by alloying during the 1960""s, there have been very few reports of Si tunneling structures since that time. The Esaki diodes were studied extensively until the mid-1960""s, setting a PVCR standard of 3.8 [5] which was only recently surpassed by Duschl et al. [6-7].
Advances in non-equilibrium epitaxial processing techniques such as molecular beam epitaxy (MBE) in the 1970""s lead to the development of III-V-based resonant tunneling diodes (RTD) [8,9], establishing a renewed interest for augmenting existing circuitry with tunnel diodes. Tunneling in an RTD occurs when the energy of electrons at the electrode coincides with the energy level of confined states in a quantum well such that energy and momentum are conserved. This condition is known as resonance.
However, an n-type RTD is not particularly feasible to build in Si. A number of groups in the early 1990""s investigated Si/SiGe RTDs based on hole transport, but the results were marginal [10,11] at room temperature. Ismail et al. attempted to circumvent this problem by growing the tunnel diodes on a relaxed SiGe layer [12]. This valiant attempt to develop a working RTD, however, only produced a PVCR of only 1.2 at room temperature.
In the late 1980""s the resonant interband tunnel diode (RITD), a hybrid between Esaki diodes and RTDs, was first proposed by Sweeny and Xu [13]. The standard RITD is a bipolar device with quantum wells defined on opposite sides of a tunnel barrier in both the p and n type regions. As the device is forward biased, the electron states in the n-side quantum well and hole states in the p side quantum well are in resonance, and the current increases. As the device is biased beyond the peak voltage, the states are no longer in resonance, and NDR will occur. If the wells are deep enough to allow for multiple states, it is theoretically possible to observe the presence of a weak second NDR region. As with the Esaki diode, once the device is biased beyond the built-in potential, the current will increase due to the onset of diffusion current. Also, for a standard double quantum well p-n RITD, NDR will only be observed under forward bias.
Sweeny and Xu suggested a number of methods for defining quantum wells in an RITD [13]. One type of device uses narrow gap materials to define a type I heterojunction double quantum well. Reports of double quantum well RITDs using InAlAs/InGaAs have demonstrated PVCRs as high as 144, the highest of any existing tunnel diode technology to date [14]. A second device uses type II heterojunctions to define the quantum well. One example of this structure is an InAs/AlSb/GaSb RITD. Since the conduction band of InAs lies below the valence band of GaSb, quantum wells may be formed without high doping. Carriers would then tunnel from confined states between the InAs/InSb conduction band well. The use of a double barrier has been shown to enhance the PVCR [14,15] experimentally.
A third device, which is essentially a hybrid between an Esaki diode and an RTD, incorporates xcex4-doping planes on either side of the p-n junction to define the quantum states for the majority carrier. This device will be the template of choice for the experimental work in the invention. III-V RITDs incorporating this structure have demonstrated PVCRs as high as 5.0 [16].
To achieve xcex4-doping requires careful control of surface segregation and interdiffusion effects to exceed the solid solubility limit of many dopants. Surface segregation is a phenomenon that occurs when the number of impurities arriving at the substrate during growth exceed the equilibrium solid solubility at the surface leading to a buildup of impurities on the growth surface. Doping in Si-MBE at growth temperatures greater than 450xc2x0 C. is well known to suffer from surface segregation [17]. A number of studies in the 1980s/1990s have demonstrated the occurrence of this phenomenon in Si for common p-type dopants (Ga [18], In [19], and B [20]) as well as for the n-type dopant Sb [21]. A region of doping impurities contained within a two dimensional plane of the epitaxial layer is known as a xcex4-doping plane of dopants.
Essentially, the growth of a xcex4-doping plane is nothing more than a stop growth. Schubert outlines the following 3 steps to the realization of a xcex4-doping layer [22]: (i) suspend epitaxial growth, (ii) allow a flux consisting only of dopants to impinge on the semiconductor surface, and (iii) resume growth of the epitaxial layer. In the idealized case where the sticking coefficient is nearly unity, and very little diffusion or segregation occurs, the dopants will be confined to the atomic plane.
In reality, the growth of a xcex4-doping layer is kinetically limited. Phenomena such as segregation and diffusion will result in undesirable broadening of the xcex4-doping planes. Schubert defines a true xcex4-doping plane to be a spike with a full width at half maximum less than 2.5 nm [22]. The key to achieving such a profile is suppressing segregation and diffusion by removing the energy required to make these phenomena favorable. The low temperature growth techniques described earlier were shown to do just this, and will therefore be useful for the realization of xcex4-doping planes. A possibility for controlling doping profiles is reducing segregation and diffusion, two kinetically mediated phenomena. Since both segregation and diffusion rely on the substrate temperature, a possibility for suppressing these mechanisms is to reduce the growth temperature until neither mechanism is probable. Growth at reduced temperatures, however, will almost certainly produce films of increased defect densities.
The first approach to growing abrupt xcex4-doping profiles to show promise among the Si community was solid phase epitaxy (SPE). In SPE, growth takes place at room temperature. This leads to two results: monotonically abrupt doping profiles and an amorphous epitaxial layer. All segregation is suppressed, as is in-situ diffusion. A post growth anneal is performed to re-crystallize the layer. One problem with SPE is that electrical activity falls below unity, particularly for Sb [23]. This implies that some Sb species have clustered during growth into complexes that act as defect sites. Since the undesirable excess current component of tunnel diodes is believed to be defect mediated, highly defected growth is unacceptable for tunnel diode growth.
While low temperature molecular beam epitaxy (LT-MBE) will not allow for profiles as sharply defined as those formed by SPE, it is sufficient to substantially suppress dopant segregation. A study by Hobart et al. illustrates this point [24]. In this experiment, a monolayer of Sb was deposited on a Si surface at various substrate temperatures to study segregation. A 100 nm Si cap was then grown on top of the Sb at the same growth temperature as the Sb monolayer. In that study is shown the secondary ion mass spectrometry (SIMS) profiles which resulted. The evidence of segregation is clear at high growth temperatures as the Sb profile is asymmetrically broadened toward the surface. Consequently, the resulting height of the xcex4-doping spike is very low. The trend with lowered temperatures was two fold: both the doping height and abruptness improved substantially. Even the excellent results at 320xc2x0 C., however, still suffer from moderate segregation.
Achieving sharp, arbitrary n-type doping profiles during Si and SiGe MBE is challenging and several approaches have been investigated to overcome the high surface segregation ratio of P, As, and Sb [25]. Such approaches include LT-MBE [24], xe2x80x9cbuild-upxe2x80x9d and xe2x80x9cflash-offxe2x80x9d [26], and in-situ ion implantation [27]. Each has its limitations and for the latter technique it is one primarily of cost and complexity. Low temperature epitaxy (LTE) is a simple technique where the low growth temperature kinetically limits surface segregation processes. Film quality is however compromised in return for achieving active Sb doping levels in excess of 5xc3x971020 cmxe2x88x923. LTE is most useful for producing low resistance contact layers since these layers are typically grown last in the layer sequence and do not jeopardize the integrity of preceding layers. Surface segregation of n-type dopants decreases significantly at low temperature but still exists and leads to a significant segregation xe2x80x9ctailxe2x80x9d following growth of the xcex4-doped layer. Build-up and flash-off techniques were employed in the infancy of Si MBE and as the terms simply involve building up certain coverage of dopant on the surface during a growth interruption, growing a given Si film thickness, and finally raising the substrate temperature to desorb the excess dopant. The technique indeed produces sharp doping profiles although the high temperature step leads to undesirable dopant diffusion and constrains the maximum carrier concentration to solid solubility limits [28]. For the tunnel diodes described here reducing diffusion is advantageous.
The strong temperature dependence of the surface segregation ratio has been exploited to obtain sharp n-type xcex4-doped layers without the parasitic dopant tail. The measured surface segregation ratio, r (ratio of surface, NSurf, to bulk, NBulk, dopant concentrations), of Sb in Si as a function of growth temperature. The surface segregation can be manipulated over 320-550xc2x0 C. for a potential four-orders-of-magnitude reduction in dopant incorporation. Additionally, there is a second effect that reduces the surface segregation ratio by up to a factor of ten: high dopant surface coverages reduce the surface free energy and the driving force for surface segregation leading to self-limiting segregation phenomenon [29]. This effect lowers the low temperature (xe2x89xa6400xc2x0 C.) r value by nearly ten times for surface concentrations exceeding 2xe2x88x923xc3x971014 cm xe2x88x922 [24]. In this invention, these phenomena are exploited and low temperatures are employed to incorporate Sb into xcex4-doped layers. The dopant tail is virtually eliminated by cycling to moderate substrate temperatures that considerably reduce Sb incorporation inducing residual dopant to xe2x80x9cfloatxe2x80x9d on the growing surface while simultaneously minimizing dopant diffusion.
The traditional view of MBE was that a limiting epitaxial temperature, TE, existed [30]. It was believed that growth below this temperature (taken to be 400xc2x0 C.) could not be crystalline or device quality. D. Eaglesham, H. J. Gossmann, and E. F. Schubert have introduced a new theory stating that for a given growth temperature, growth will initially proceed in a crystalline fashion until some critical thickness, hepi is reached [31]. Beyond hepi, the film will first become poly-crystalline, and then will become amorphous. Amazingly even for growth at 100xc2x0 C., it is possible to grow several crystalline atomic monolayers. When the temperature is elevated to 320xc2x0 C. (the temperature shown by Hobart to suppress Sb segregation [24]), this thickness is increased to 150 nm.
One method for characterizing the existence of this thickness is via oscillations in reflective high-energy electron diffraction (RHEED) patterns during growth. It has been shown that strong oscillations in intensity correspond to layer-by-layer growth; layers showing damped oscillations are of poor crystalline quality [32,33]. Growth at temperatures as low as 220xc2x0 C. clearly results in strong RHEED oscillations. Growth at 50xc2x0 C. shows severely damped oscillations, suggesting that 50xc2x0 C. will not yield a good film.
Films grown by SPE suffer from incomplete dopant activation. In this regard, LT-MBE is superior to SPE. Sb doped films grown at 270xc2x0 C. show unity activation for doping concentrations as high as 5xc3x971020 cmxe2x88x923 [34]. B films grown at the same temperature show unity activation above 1021 cmxe2x88x923 [35]. Clearly if the doping level is a more stringent requirement than the sharpness of the spike, LT-MBE is a preferable approach.
Of course, it is expected that films grown by LT-MBE will have more defects than those grown by standard MBE temperatures. It is believed that LT-MBE leads to the presence of vacancy-like defects throughout the film [36]. One approach to removing these defects is annealing the samples in an RTA furnace.
Simple device applications have shown the benefit of introducing a post growth anneal. Gossmann et al demonstrated a pair of p-n junction diodes grown at 220xc2x0 C. with doping levels in the mid-1017 cmxe2x88x923 range on either side of the junction [34]. Samples annealed at 450xc2x0 C. were found to have an ideality factor of 1.94, indicating a heavily defected layer. Samples annealed at 600xc2x0 C. were found to have significantly improved ideality factors of 1.05. This evidence suggests that the RTA served to remove many of the defects in the film, thereby leading to improved device performance.
Another approach has been developed by Jorke et al. [37,38]. Their structure consisted of a p+-i-n+ junction and grown at 325xc2x0 C. The p+ region was doped 3xc3x971019 cmxe2x88x923, and the n+ region was doped 1xc3x971020 cmxe2x88x923. When the i-region is reduced to 5-10 nm, room temperature NDR was observed with a PVCR of two.
An alternate approach has been developed by Morita et al. [39,40]. Their structure is an interband tunnel Esaki tunnel diode being developed for low power memory applications. The structure consists of a degenerately doped substrate region, a thin SiO2 tunnel barrier, and an amorphous contacting region. The relative simplicity of the structure and use of an SiO2 tunnel barrier makes it immediately compatible with a CMOS process. Because the oxide has a large band offset in the conduction band, the thermal currents in this structure will be highly reduced. Theoretically, this should result in elevated PVCR. However, the highest PVCR observed by this group is approximately 1.8 at an ultra low current density of 3xc3x9710xe2x88x926A/cm2.
A final approach was developed by Zhu et al. [41,42], where a p+ xcex4-doping layer (3xc3x971013 cmxe2x88x922) was first grown, followed by 4 nm of undoped Si and an n+ xcex4-doping layer (1xc3x971014 cmxe2x88x922). The entire structure was grown around 500-550xc2x0 C., which was too high and led to deleterious dopant segregation and diffusion. No room temperature NDR was observed.
The present invention presents the first demonstration of room temperature negative differential resistance (NDR) in an epitaxially grown Si based Resonant Interband Tunnel Diode [43-52]. The previous discussion has shown that the possibility of realizing this structure may be achieved by controlling of the dopant distributions by LT-MBE growth followed by a post-growth anneal. Based on this principle, nearly every design presented in the remainder of this invention includes at least one of the features listed below:
An intrinsic tunneling barrier;
xcex4-doped injectors to create confined quantum states;
Offsets of the xcex4-doping planes from the heterojunction interfaces to minimize dopant outdiffusion;
Low temperature molecular beam epitaxial growth (LT-MBE); or
Post-growth rapid thermal annealing (RTA) for dopant activation and/or point defect reduction.
The variation in xcex4-doping placement was chosen because of two issues relevant to the RITDs of this study: the effects of growth interruption and dopant outdiffusion. A xcex4-doped layer is in essence a stop-growth. Stop-growths are commonly employed to smoothen the growth front profile and reduce heterojunction roughness [53,54]. During a stop-growth, the growth rate drops considerably, but the impurity accumulation rate rises dramatically, which has been shown to quench quantum well photoluminescence [54]. Also, dopant outdiffision from the xcex4-doped spike is expected to be preferentially oriented towards the undoped central SiGe spacer, rather than the highly doped outer Si injector layers, due to the concentration gradient. Furthermore, Sb diffusion [55,56] has been shown to be enhanced with increased Ge content whereas B diffusion [57] has been shown to be suppressed with the addition of Ge. Thus, the placement of the xcex4-doped layers offset from the SiGe spacer using undoped Si reduces these effects and provides a higher quality tunneling barrier with reduced defects and higher PVCR.
The present invention provides a Si-based tunnel diode that uses a planar process suitable for integration with CMOS or Si/SiGe heterojunction bipolar technology.
The present invention also provides a Si-based tunnel diode that shows room temperature negative differential resistance (NDR).
Additional advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the appended claims.
The present invention provides a family of Si compatible tunnel diode structures. In general, the diodes are defined by forming an N+ (or P+) contact layer, an N+ (or P+) injection layer, a tunnel barrier (doped or undoped) sandwiched between spacer layers (doped or undoped), a P+ (or N+) injection layer, and a P+ (or N+) contact layer.
The present invention further provides a class of the aforementioned tunnel diodes such that the structure is defied by an N+ (or P+) contact layer, an N+ (or P+) injection layer, a tunnel barrier (doped or undoped) sandwiched between a pair of spacer layers (doped or undoped), a quantum well (the quantum well may be defined by delta doping, band discontinuities resulting from heterojunction interfaces, superlattices, or a combination thereof), a P+ (or N+) injection layer, and a P+ (or N+) contact layer.
According to a preferred embodiment, there is a variation of the aforementioned tunnel diodes differentiated by the presence of a quantum well on either side of the tunnel barrier. The structure comprising of a P+ (or N+) contact layer, a P+ (or N+) injection layer, a quantum well (the quantum well may be defined by delta doping, band discontinuities resulting from heterojunction interfaces, superlattices, or a combination thereof), a tunnel barrier (doped or undoped) sandwiched between a pair of spacer layers, a quantum well (the quantum well may be defined by delta doping, band discontinuities resulting from heterojunction interfaces, superlattices, or a combination thereof), an N+ (or P+) injection layer, and an N+ (or P+) contact layer.
An additional embodiment of the invention results from the growth of a pnp (or npn) tunnel diode with dual tunnel barriers. One feature of this layer is that its electrical characteristics are symmetrical with applied bias, resulting in the onset of negative differential resistance in the forward and reverse directions. The structure is defined by a P+ (or N+) ohmic contact layer, a P+ (or N+) injection layer, a quantum well (the quantum well may be defined by delta doping, band discontinuities resulting from heterojunction interfaces, superlattices, or a combination thereof) in the valence (or conduction) band with, a tunnel barrier (doped or undoped) sandwiched between a pair of spacer layers (doped or undoped), a quantum well (the quantum well may be defined by delta doping, band discontinuities resulting from heterojunction interfaces, superlattices, or a combination thereof) in the conduction (or valence) band with, a second tunnel barrier (doped or undoped) sandwiched between a pair of spacer layers (doped or undoped), a quantum well (the quantum wee may be defined by delta doping, band discontinuities resulting from heterojunction interfaces, superlattices, or a combination thereof) in the valence (or conduction) band with, a P+ (or N+) injection layer, and a P+ (or N+) contact layer.
Further, embodiments of the present invention describe the post-growth heat treatment of the aforementioned structural embodiments, and the resulting influence on the current-voltage characteristics.
Further, embodiments of the present invention the epitaxial growth and thermal cycling necessary to realize the aforementioned structural embodiments.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.